Network equipment test devices transmit and receive packets at line rates to test the performance and functionality of network equipment. Line rate refers to the data transfer speed supported by the physical layer interface to the communications medium. For example, for 40 gigabit Ethernet, the line rate is 40 Gb/s.
Although the physical layer chips (PHYs) are capable of transmitting and receiving bits over the communications medium at line rates, the field programmable gate arrays (FPGAs) used to process transmitted and received bits often cannot do so at a speed necessary to keep up with line rate transmission and reception. To address this issue, one design approach taken by FPGA developers involves the implementation of architectures that parallelize processing tasks that are to be performed by FPGA devices. One possible parallelization strategy involves increasing the width of the internal communications bus that is used transmit and receive data and using plural FPGA devices to process different segments of the bus in parallel during each clock cycle.
On the receive side, FPGAs can be used in parallel to scan the data bus for patterns known to be present in received data. However, using FGPA devices in parallel can require complex logic circuit design and duplicate logic circuit components to detect patterns of bits on the data bus. The logic design can increase in complexity and numbers of required components to account for cases were more than one packet is present on the bus during one clock cycle and when a matching pattern spans more than one clock cycle. Accordingly, there exists a need for methods, systems, and computer readable media for wide bus pattern matching.